A typical electrically erasable programmable read-only memory (EEPROM) cell includes two MOS transistors connected in series. An EEPROM of this kind is shown schematically in FIG. 1 and structurally in FIG. 2. It includes a select transistor 10 and a sense transistor 11, which are connected in series between a bit line 13 and an array ground 17. The gate of select transistor 10 is connected to a row line 12. Sense transistor 11 is controlled by a memory gate 16 and a floating gate 15. When the state of the cell is to be read, select transistor 10 is turned on via a voltage applied to row line 12, and a read voltage is applied to bit line 13 to determine the conductive state of sense transistor 11. If sense transistor 11 is conductive (programmed) a current will flow; if it is non-conductive (erased) a current will not flow.
Sense transistor 11 is programmed or erased by applying an appropriate voltage between memory control gate 16 and bit line 13, with select transistor 10 turned on. If memory control gate 16 is grounded and a positive programming voltage (typically about 14.5 V) is applied to bit line 13, electrons tunnel from floating gate 15 through a very thin tunnel oxide layer 18 (shown in FIG. 2) to the N.sup.+ region designated 14 in FIG. 2, leaving floating gate 15 with a net positive charge. In this state, the cell is programmed. If bit line 13 is grounded and a positive programming voltage is applied to memory control gate 16, the reverse occurs. Electrons tunnel from N.sup.+ region 14 through the very thin oxide layer 18 into floating gate 15, leaving floating gate 15 with a net negative charge. In this state, the cell is erased.
The charge on floating gate 15 determines the threshold voltage of sense transistor 11. If floating gate 15 is positively charged, sense transistor 11 has a relatively low threshold voltage V.sub.TL. If floating gate 15 is negatively charged, sense transistor 11 has a relatively high threshold voltage V.sub.TH. Normally, a reference voltage V.sub.ref about halfway between V.sub.TH and V.sub.TL is applied to memory control gate 16. Thus, if sense transistor 11 has been programmed, it will be conductive; if it has been erased, it will be an open circuit.
It is desirable to have the margin between V.sub.TH and V.sub.TL be as large as possible because a large margin provides for a strong cell current and longer data retention.
For a particular tunnel oxide layer thickness, the margin is primarily determined by two factors: (i) the coupling ratio and (ii) the voltage difference between memory control gate 16 and the common point between sense transistor 10 and select transistor 11 when the cell is being programmed or erased. The latter in turn is proportional to the voltage difference applied between cell memory control gate 16 and bit line 13. With smaller cells and greater cell densities, both of these factors have a tendency to reduce the margin. The coupling ratio is established by the layout of the cell, and a smaller layout tends to reduce the coupling ratio. As explained below, smaller cell dimensions also tend to limit the voltage difference that can be used in programming and erasing the cell.
FIG. 3 illustrates V.sub.TH and V.sub.TL as a function of the potential difference (V.sub.pp) between the memory control gate and the bit line during the erase and programming operations, respectively. As FIG. 3 indicates, V.sub.TH increases with increasing V.sub.pp and V.sub.TL decreases with increasing V.sub.pp. Thus, the margin (V.sub.TH -V.sub.TL) also increases as V.sub.pp increases.
The desire for a large margin is in conflict with the increasing miniaturization of EEPROM cells. With thinner oxides, tighter design rules and more highly doped and shallower junctions, breakdown voltages such as punch through, field-aided junction breakdown, and field device turn on tend to decrease. For example, referring to FIG. 2, as the thickness of gate oxide 20 decreases, the field-aided junction breakdown voltage (BV.sub.DSS) of select transistor 10 decreases as a result of breakdown at the PN junction in the area designated 21 in FIG. 2. Thus, while a thinner gate oxide has the beneficial effect, for example, of increasing the transconductance (G.sub.m) in select transistor 10, the price of greater transconductance is a lower BV.sub.DSS. This in turn limits the voltage which can be used in programming or erasing the cell and makes it more difficult to obtain a wide margin. The relationship between G.sub.m and BV.sub.DSS, respectively, and the thickness of gate oxide 20 is illustrated in FIG. 4.